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Single-chip Type with Built-in FET Switching Regulator Series
High-efficiency Step-up/down Switching Regulators with Built-in Power MOSFET
BD8305MUV
No.10027EDT08
Description ROHM's highly-efficient step-up/down switching regulator BD8305MUV produces step-up/down output including 3.3 V from 1 cell of lithium battery with just one coil.This IC adopts an original step-up/down drive system and creates a higher efficient power supply than conventional Sepic-system or H-bridge system switching regulators. Features 1) Highly-efficient step-up/down DC/DC converter to be constructed just with one inductor. 2) Input voltage 2.5 V - 5.5 V 3) Output current 1 A at 3.3 V 800 mA at 5.0 V 4) Incorporates soft-start function. 5) Incorporates timer latch system short protecting function. 6) High heat radiation surface mounted package VQFN020V4040 Application General portable equipment like portable audio or DSC/DVC Absolute Maximum Ratings Parameter Maximum applied power voltage Maximum input current Maximum input voltage Power dissipation Operating temperature range Storage temperature range Junction temperature Symbol Vcc,PVCC Iinmax Lx1 Lx2 Pd Topr Tstg Tjmax BD8305MUV 7.0 2.0 7.0 7.0 700 -25 to +85 -55 to +150 150 Unit V A V V mW C C C
*1 When installed on a 70.0 mm x 70.0 mm x 1.6 mm glass epoxy board. The rating is reduced by 5.6 mW/C at Ta = 25C or more.
Operating Conditions (Ta = 25C) Parameter Power supply voltage Output voltage
Symbol Vcc OUT
Voltage range 2.5 to 5.5 2.8 to 5.2
Unit V V
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1/15
2010.05 - Rev.D
BD8305MUV
Electrical Characteristics (Unless otherwise specified, Ta = 25 C, VCC = 3.7 V) Parameter Symbol Min 50 0.8 0.790 -50 0.6 10 0.7 77 1.6 -1 -1 1.5 -0.3 250 Target Value Typ 2.25 100 1.0 0.800 0 1.00 20 1.5 85 120 100 120 100 2.4 0 0 400 500 10 Max 2.45 150 1.2 0.810 50 1.4 30 3.0 100 93 200 160 200 160 1 1 5.5 0.3 700 1 1 1 750 20 Unit
Technical Note
Conditions
[Low voltage input malfunction preventing circuit] Detection threshold voltage VUV Hysteresis range VUVhy [Oscillator] osc Oscillation frequency [Error AMP] INV threshold voltage VINV Input bias current IINV Soft-start time Tss Output source current IEO Output sink current IEI [PWM comparator] LX1 Max Duty Dmax1 LX2 Max Duty Dmax2 [Output] LX1 PMOS ON resistance RON1p LX1 NMOS ON resistance RON1n LX2 PMOS ON resistance RON2p LX2 NMOS ON resistance RON2n LX1 OCP threshold Iocp LX1 leak current I leak1 LX2 leak current I leak2 [STB] Operation VSTBH STB pin control voltage No-operation VSTBL STB pin pull-down resistance RSTB [Circuit current] VCC pin ISTB1 Standby current PVCC pin ISTB2 VOUT pin ISTB3 Circuit current at operation VCC Icc1 Circuit current at operation PVCC Icc2
V mV MHz V nA msec uA mA % % m m m M A uA uA V V k uA uA uA uA uA
Vcc monitor
RT=47k
Vcc=7.0V , VINV=3.5V RT=47k VINV=0.5V , VFB =1.5V VINV=1.1V , VFB =1.5V
VGS=3.0V VGS=3.0V VGS=3.0V VGS=3.0V PVCC=3.0V
VINV=1.2V VINV=1.2V
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2/15
2010.05 - Rev.D
BD8305MUV
Description of Pins
Lx1 PGND
Technical Note
PVCC
Pin No. 1 2 34
10 9 8 7 6
VOUT Lx2 PGND
Pin Name FB INV GND VOUT Lx2 PGND Lx1 PVCC VCC STB RT
Function Error AMP output terminal Error AMP input terminal Ground terminal Output voltage terminal Output side coil connecting terminal Power transistor ground terminal Input side coil connecting terminal DC/DC converter input terminal Control part power supply input terminal ON/OFF terminal Oscillation frequency set terminal
15 14 13 12 11
PVCC
16 17
56 78 912 1314 1517 18
VCC 18 STB 19 RT
20 1
FB
2
INV
3
4
GND
5
VOUT
19 20
Fig. 1 Pin layout
Block Diagram
STB
RT
PVCC VCC
STBY_IO
Reference
VREF
UVLO PRE DRIVER TIMMING CONTROL PRE DRIVER
GND
FB H
q
SCP
16000 ount
OSC
STOP
LX1
PWM CONTROL
FB
TIMMING CONTROL PRE DRIVER
ERROR_AMP + + -
VREF Soft Start
PRE DRIVER
PGND
INV
VOUT
LX2
Fig. 2 Block diagram
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3/15
2010.05 - Rev.D
BD8305MUV
Description of Blocks 1.VREF This block generates ERROR AMP reference voltage.The reference voltage is 0.8 V.
Technical Note
2.UVLO Circuit for preventing low voltage malfunction Prevents malfunction of the internal circuit at activation of the power supply voltage or at low power supply voltage. Monitors VCC pin voltage to turn off all output FET and DC/DC converter output when VCC voltage is lower than 2.2 V, and reset the timer latch of the internal SCP circuit and soft-start circuit. 3.SCP Timer latch system short-circuit protection circuit When the INV pin is the set 0.8 V or lower voltage, the internal SCP circuit starts counting. The internal counter is in synch with OSC, the latch circuit activates after the counter counts about 8200 oscillations to turn off DC/DC converter output (about 8.2 msec when RT =47K). To reset the latch circuit, turn off the STB pin once. Then, turn it on again or turn on the power supply voltage again. 4.OSC Oscillation circuit to change frequency by external resistance of the RT pin (20 pin). When RT = 47 k, operation frequency is set at 1 MHz. 5.ERROR AMP Error amplifier for detecting output signals and output PWM control signals. The internal reference voltage is set at 0.8 V. 6.PWM COMP Voltage-pulse width converter for controlling output voltage corresponding to input voltage. Comparing the internal SLOPE waveform with the ERROR AMP output voltage, PWM COMP controls the pulse width and outputs to the driver. Max Duty and Min Duty are set at the primary side and the secondary side of the inductor respectively, which are as follows: Primary side (Lx1) Max Duty : 100 %, Min Duty : 0% Secondary side (Lx2) Max Duty : 100 %, Min Duty : About 15 % 7.SOFT START Circuit for preventing in-rush current at startup by bringing the output voltage of the DC/DC converter into a soft-start Soft-start time is in synch with the internal OSC, and the output voltage of the DC/DC converter reaches the set voltage after about 1000 oscillations (About 1 msec when RT = 47 k). 8.PRE DRIVER CMOS inverter circuit for driving the built-in Pch/Nch FET.Dead time is provided for preventing feedthrough during switching.The dead time is set at about 15 nsec for each individual SWs. 9. STBY_IO Voltage applied on STB pin (19 pin) to control ON/OFF of IC. Turned ON when a voltage of 1.5 V or higher is applied and turned OFF when the terminal is open or 0 V is applied. Incorporates approximately 400 k pull-down resistance. 10. Pch/Nch FET SW Built-in SW for switching the coil current of the DC/DC converter. Pch FET is about 120mand Nch is 100m. Since the current rating of this FET is 2A,it should be used within 1.6A in total including the DC current and ripple current of the coil.
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4/15
2010.05 - Rev.D
BD8305MUV
Reference Data (Unless otherwise specified, Ta = 25C, VCC = 3.7 V)
Technical Note
0.810
0.810
1.20 UVLO 1.15 1.10
0.805 INV THRESHOLD [V]
INV THRESHOLD [V]
0.805
0.800
VCC=3.7V VCC=2.4V VCC=5.5V VCC=7.0V
0.800
0.795
0.795
0.790 -50 0 50 100 150 TEMPERATURE []
0.790 0.0 2.0 4.0 6.0 8.0
FREQUENCY [MHz]
1.05 1.00 0.95 0.90 0.85 0.80 -50 0 50 100 150
VCC [V]
TEMPERATURE []
Fig.3 INV threshold
1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 2 3 4 5 6
Fig.4 INV threshold (power supply property)
2.6 2.5 2.4 2.0 1.8
Fig.5 Oscillation frequency
INV=1.1V
RESET
FB SINK CURRENT [mA]
150
UVLO THRESHOLD [V]
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
FREQUENCY [MHz]
2.3 2.2 2.1 2.0 1.9 1.8 -50 0 50 100
DETECT
0.0 0 1 2 3 4
VCC []
TEMPARATURE []
FB VOLTAGE [V]
Fig.6 Oscillation frequency
Fig.7 UVLO threshold
Fig.8 FB sink current
(power supply property)
0 -5
INV=0.5V
300
Io=500mA
300
Io=500mA
250
250
VCC=2.0V VCC=3.0V VCC=3.7V VCC=6.0V
FB SOURCE CURRENT [uA]
ON RESISTANCE [m]
-15 -20 -25 -30 -35 -40 0.0 0.5 1.0 FB VOLTAGE [V] 1.5 2.0
200 150 100 50 0 -60
ON RESISTANCE [m]
-10
200
VCC=6.0V
150 100 50 0
VCC=2.0V
VCC=3.0V
VCC=3.7V
-10
40
90
140
-60
-10
40
90
140
TEMPERATURE []
TEMPERATURE []
Fig.9 FB source current
Fig.10 Lx1 Pch FET ON resistance
Fig.11 Lx1 Nch FET ON resistance
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5/15
2010.05 - Rev.D
BD8305MUV
Technical Note
300
Io=500mA
300
Io=500mA
1000
INV=1.1V
250
250
800
ON RESISTANCE [m]
ON RESISTANCE [m]
VCC=2.0V
VCC=3.0V VCC=3.7V VCC=6.0V
VCC CURRENT [uA]
200 150 100 50 0 -60
200
VCC=6.0V
600
150 100 50 0
VCC=2.0V
VCC=3.0V VCC=3.7V
400
200
-10
40
90
140
-60
-10
40
90
140
0 0 1 2 3 4 5 6 7
TEMPERATURE []
TEMPERATURE []
VCC VOLTAGE [V]
Fig.12 Lx2 Pch FET ON resistance
Fig.13 Lx2 Nch FET ON resistance
Fig.14 VCC input current
5.0
20 20
4.5
OCPdetectthreshold [A]
INV=1.1V
INV=1.1V
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
15
15
PVCC CURRENT [uA]
10
VOUT CURRENT [uA]
10
5
5
0 0 1 2 3 4 5 6 7
0 0 1 2 3 4 5 6 7
-25
0
25
50
75
100
TEMPERATURE []
PVCC VOLTAGE [V]
VOUT VOLTAGE [V]
Fig.15 PVCC input current
Fig.16 VOUT input current
Fig.17 OCP detect threshold -Ta
5.0 4.5 4.0
OCP detect threshold [A]
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCC VOLTAGE [V]
Fig.18 OCP detect threshold -VCC
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6/15
2010.05 - Rev.D
BD8305MUV
Example of Application1
10uF(ceramic) murata GRM31CB11A106KA01
Technical Note
Input: 2.8 to 5.5 V, output: 3.3 V / 1.0 A, frequency 600 kHz
2.85.5V
15
PVCC
14
Lx1
13
Lx1
12
PGND
11
PGND
16
RVIN
PVCC
10
PGND
4.7uH TOKO DE3518C
17
PVCC
PGND
9
18
VCC
Lx2
8
ON/OFF
19
STB
Lx2
7
10uF(ceramic) murata GRM31CB11A106KA01
GND
82k
1
INV
2
3
GND
FB
20
RT
VOUT
VOUT
6
3.3V/1.0A
4
5
CVCC 1uF
CFB 1500p
CC 150p RINV1 75k RC 5.1k
RFB 7.5k
Fig.19 Example of Application1 Example of Application2 Input: 2.8 to 5.5 V, output: 4.0 V / 1.0 A, frequency 1MHz
10uF(ceramic) murata GRM31CB11A106KA01
RINV2 24k
2.85.5V
15
PVCC
14
Lx1
13
Lx1
12
PGND
11
PGND
16
RVIN
PVCC
10
PGND
4.7uH murata LQH32PN4R7N
17 PVCC
PGND
9
18
VCC
Lx2
8
ON/OFF
19
STB
Lx2
7
22uF(ceramic) murata GRM21BB30J226ME38
GND
INV
GND
FB
20 RT
47k
VOUT
VOUT
6
1
2
3
4
5
4.0V/1.0A
CVCC 1uF
CFB 1500p
CC 150p RINV1 120k RINV2 30k RC 5.1k
RFB 7.5k
Fig.20 Example of Application2
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7/15
2010.05 - Rev.D
BD8305MUV
Example of Board Layout
Technical Note
GND VBAT
CVCC
Lx1
CVIN
L
CVOUT
RVCC
VCC
Lx2
PGND
VOUT
GND
Fig.21 Example of Board Layout
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RINV1
RT CFB RFB RC CC
1pin
VOUT
RINV2
8/15
2010.05 - Rev.D
BD8305MUV
Reference Application Data (Example of application 1)
100 90 80 70 EFFICIENCY [%] 60 50 40 30 20 10 0 1 10 100 1000 OUTPUT CURRENT [mA]
3.27 2.0 3.0 4.0 5.0 6.0 3.27 1 10 3.33 3.33
Technical Note
VBAT=2.8V
3.32
Io=600mA
3.32
VBAT=3.7V
OUTPUT VOLTAGE [V]
OUTPUT VOLTAGE [V]
3.31 3.30 3.29 3.28
3.31 3.30 3.29 3.28
VBAT=3.7V
VBAT=4.2V
100
1000
INPUT VOLTAGE [V]
OUTPUT CURRENT [mA]
Fig.22 Power conversion efficiency
Fig.23 Line regulation
Fig.24 Load regulation
(Example of application2)
2000 1800 1600
100 90 80 70 E FFICIE NCY [%] 60 50 40 30 20
VBAT=2.8V
4.08 4.06
Io=600mA
1400 Iomax{mA] 1200 1000 800 600 400
VBAT=3.7V
OUTPUT VOLTAGE [V]
4.04 4.02 4.00 3.98 3.96 3.94 3.92
VBAT=4.2V
10
200 0 2.5 3.0 3.5 4.0 VBAT[V] 4.5 5.0 5.5
0 1 10 100 OUTPUT CURRNET [mA] 1000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE [V]
Fig.25 Maximum output current
Fig.26 Power conversion efficiency
Fig.27 Line regulation
4.08 4.06 4.04
VBAT=3.7V
OUTPUT VOLTAGE [V]
4.02 4.00 3.98 3.96 3.94 3.92 1 10 100 1000
OUTPUT CURRENT [mA]
Fig.28 Load regulation
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9/15
2010.05 - Rev.D
BD8305MUV
Technical Note
Selection of Parts for Applications (1) Output inductor A shielded inductor that satisfies the current rating (current value, Ipeak as shown in the drawing below) and has a low DCR (direct current resistance component) is recommended. Inductor values affect output ripple current greatly. Ripple current can be reduced as the coil L value becomes larger and the switching frequency becomes higher as the equations shown below.
IL
Ipeak =Iout x(Vout/VIN) / IL/2 [A] (Vin-Vout) IL= L |(Vin-Vout)| IL= L (Vout-Vin) L x x x Vout Vin x 1 f
(1) Fig. 29 Ripple current [A] (in step-down mode) 1 x f (2)
Voutx2x0.85 (Vin+Vout) Vin x 1 f
[A] (in step-up/down mode)
(3)
IL=
Vout
[A] (in step-up mode)
(4)
(: Efficiency, IL: Output ripple current, f: Switching frequency) As a guide, output ripple current should be set at about 20 to 50% of the maximum output current. Current over the coil rating flowing in the coil brings the coil into magnetic saturation, which may lead to lower efficiency or output oscillation. Select an inductor with an adequate margin so that the peak current does not exceed the rated current of the coil. (2) Output capacitor A ceramic capacitor with low ESR is recommended for output in order to reduce output ripple. There must be an adequate margin between the maximum rating and output voltage of the capacitor, taking the DC bias property into consideration. Output ripple voltage when ceramic capacitor is used is obtained by the following equation. Vpp=ILx 1 2xfxCo ILxRESR [V] (5)
Setting must be performed so that output ripple is within the allowable ripple voltage. (3) Setting of oscillation frequency Oscillation frequency can be set using a resistance value connected to the RT pin (1 pin). Oscillation frequency is set at 1 MHz when RT = 47 k, and frequency is inversely proportional to RT value. See Fig. 30 for the relationship between RT and frequency. Soft-start time changes along with oscillation frequency. See Fig. 31 for the relationship between RT and soft-start time.
10000
10
SWITCHNG FREQUENCY [kHz]
SOFT START TIME [msec]
1000
1
100 1 10 100 1000
0.1
1 10 100 1000
RT PIN RESISTANCE [k]
RT PIN RESISTANCE [k]
Fig. 30 Oscillation frequency - RT pin resistance
Fig. 31 Soft-start time - RT pin resistance
* Note that the above example of frequency setting is just a design target value, and may differ from the actual equipment.
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10/15
2010.05 - Rev.D
BD8305MUV
(4) Output voltage setting The internal reference voltage of the ERROR AMP is 0.8 V. (8) of Fig.32.
VOUT ERROR AMP INV R2 VREF 0.8V Vo=
Technical Note
Output voltage should be obtained by referring to Equation
R1
(R1+R2) R2
x0.8 [V] (8)
Fig. 32 Setting of feedback resistance (5) Determination of phase compensation Condition for stable application The condition for feedback system stability under negative feedback is as follows: - Phase delay is 135 or less when gain is 1 (0 dB) (Phase margin is 45 or higher) Since DC/DC converter application is sampled according to the switching frequency, the GBW of the whole system (frequency at which gain is 0 dB) must be set to be equal to or lower than 1/5 of the switching frequency. In summary, target property of applications is as follows: - Phase delay must be 135or lower when gain is 1 (0 dB) (Phase margin is 45 or higher). - The GBW at that time (frequency when gain is 0 dB) must be equal to or lower than 1/5 of the switching frequency. For this reason, switching frequency must be increased to improve responsiveness. One of the points to secure stability by phase compensation is to cancel secondary phase delay (-180) generated by LC resonance by the secondary phase lead (i.e. put two phase leads). Since GBW is determined by the phase compensation capacitor attached to the error amplifier, when it is necessary to reduce GBW, the capacitor should be made larger. -20dB/decade (A) C R FB 0 PHASE [degree] -90 Fig.33 General integrator
Error AMP is a low-pass filter because phase compensation such as (1) and (2) is performed. For DC/DC converter application, R is a parallel feedback resistance.
GAIN [dB]
A
0
(B)
Phase margin 1
-180 Point (A) fp= [Hz] (9)
2RCA 1 2RC
Point (B) fGBW=
[Hz]
(10)
Fig.34 Frequency property of integrator Phase compensation when output capacitor with low ESR such as ceramic capacitor is used is as follows: When output capacitor with low ESR (several tens of m) is used for output, secondary phase lead (two phase leads) must be put to cancel secondary phase lead caused by LC.One of the examples of phase compensation methods is as follows:
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11/15
2010.05 - Rev.D
BD8305MUV
VOUT R1 C1 R3 FB R2 R4 C2 Phase lead fz1 = Phase lead fz2 = 1 2R1C1 1 2R4C2 1 Phase delay fp1 = 2R3C1 1 LC resonance frequency = Fig.35 Example of setting of phase compensation 2(LC) [Hz] [Hz] [Hz] [Hz]
Technical Note
(11) (12)
(13)
(14)
For setting of phase-lead frequency, both of them should be put near LC resonance frequency. When GBW frequency becomes too high due to the secondary phase lead, it may get stabilized by setting the primary phase delay to a frequency slightly higher than the LC resonance frequency by R3 to compensate it.
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12/15
2010.05 - Rev.D
BD8305MUV
I/O Equivalence Circuit
Technical Note
FB
INV
VCC VCC
VCC
VCC
FB
INV
VOUT,Lx2,PGND
VOUT
PVCC,Lx1,PGND
PVCC
Lx2
Lx1
VCC
VCC
PGND
PGND
STB
VCC
RT
VCC
STB VCC
RT
Fig.36 I/O Equivalence Circuit
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13/15
2010.05 - Rev.D
BD8305MUV
Technical Note
Notes for use 1) Absolute Maximum Rating We dedicate much attention to the quality control of these products, however the possibility of deterioration or destruction exists if the impressed voltage, operating temperature range, etc., exceed the absolute maximum ratings. In addition, it is impossible to predict all destructive situations such as short-circuit modes, open circuit modes, etc. If a special mode exceeding the absolute maximum rating is expected, please review matters and provide physical safety means such as fuses, etc. 2) GND Potential Keep the potential of the GND pin below the minimum potential at all times. 3) Thermal Design Work out the thermal design with sufficient margin taking power dissipation (Pd) in the actual operation condition into account. 4) Short Circuit between Pins and Incorrect Mounting Attention to IC direction or displacement is required when installing the IC on a PCB. If the IC is installed in the wrong way, it may break. Also, the threat of destruction from short-circuits exists if foreign matter invades between outputs or the output and GND of the power supply. 5) Operation under Strong Electromagnetic Field Be careful of possible malfunctions under strong electromagnetic fields. 6) Common Impedance When providing a power supply and GND wirings, show sufficient consideration for lowering common impedance and reducing ripple (i.e., using thick short wiring, cutting ripple down by LC, etc.) as much as you can. 7) Thermal Protection Circuit (TSD Circuit) This IC contains a thermal protection circuit (TSD circuit). The TSD circuit serves to shut off the IC from thermal runaway and does not aim to protect or assure operation of the IC itself. Therefore, do not use the TSD circuit for continuous use or operation after the circuit has tripped. 8) Rush Current at the Time of Power Activation Be careful of the power supply coupling capacity and the width of the power supply and GND pattern wiring and routing since rush current flows instantaneously at the time of power activation in the case of CMOS IC or ICs with multiple power supplies.
9) IC Terminal Input
This is a monolithic IC and has P+ isolation and a P substrate for element isolation between each element. P-N junctions are formed and various parasitic elements are configured using these P layers and N layers of the individual elements. For example, if a resistor and transistor are connected to a terminal as shown on Fig.37: The P-N junction operates as a parasitic diode when GND > (Terminal A) in the case of a resistor or when GND > (Pin B) in the case of a transistor (NPN) Also, a parasitic NPN transistor operates using the N layer of another element adjacent to the previous diode in the case of a transistor (NPN) when GND > (Pin B). The parasitic element consequently rises under the potential relationship because of the IC's structure. The parasitic element pulls interference that could cause malfunctions or destruction out of the circuit. Therefore, use caution to avoid the operation of parasitic elements caused by applying voltage to an input terminal lower than the GND (P board), etc. Resistor (Pin A) (Pin B) Transistor (NPN) B E C

N P N P N P Substrate P N P N
GND
N GND
Parasitic Element
Parasitic Element
P Substrate GND
Parasitic Element
Fig.37 Example of simple structure of Bipolar IC
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14/15
2010.05 - Rev.D

P
P
(Pin A)
BD8305MUV
Ordering part number
Technical Note
B
D
8
Part No.
3
0
5
M
U
V
-
E
2
Part No.
Package MUV: VQFN020V4040
Packaging and forming specification E2: Embossed tape and reel
VQFN020V4040
4.00.1

Tape
4.00.1
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
1PIN MARK
1.0MAX
S
( reel on the left hand and you pull out the tape on the right hand
)
0.08
S 2.10.1 0.5
1 20 16 15 11 5 6 10
C0.2
0.40.1
1.0
+0.05 0.25 -0.04
2.10.1
+0.03 0.02 -0.02
(0.22)
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
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15/15
2010.05 - Rev.D
Notice
Notes
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R1010A

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